The invention relates to a circuit useful in complementary metal oxide semiconductor (CMOS) structures and is particularly adapted for those involving a large number of gates fabricated into a single chip. Such arrays are known as gate arrays which are useful in fabricating logic circuits in which the gates are interconnected to achieve the desired logic function. Typically a gate array is fabricated into a silicon substrate in a mass produced wafer process. The final metallization, in which the logic function is personalized, is then tailored in accordance with the intended application. In my copending patent application, Ser. No. 321,839, now U.S. Pat. No. 4,430,582, filed Nov. 16, 1981, and titled FAST CMOS BUFFER FOR TTL INPUT LEVELS, now U.S. Pat. No. 4,430,582 a circuit is disclosed for making a large number of CMOS gates in an array conform to transistor-transistor logic (TTL) levels. The teaching in that application is incorporated herein by reference.
One of the problems in CMOS gate arrays is the mass manufacture of gates that respond to the TTL logic levels over a substantial range of power supply voltage, temperature, and transistor parameters. This is particularly true when the gate array includes elements that display hysteresis as found in the Schmitt trigger.